Microprocessor designers, system designers and system software designers often count the number of times a particular event occurs in a microprocessor to gage the performance of the microprocessor being designed. Performance counters are typically used for this purpose. Each time a particular event occurs, the associated performance counter is incremented. The performance counters are typically built into the circuits being monitored.
After the microprocessor has performed some or all of its tasks, the performance counters are read to determine the number of times a particular event occurred. For example, if the average number of instructions issued per clock cycle is of interest, a performance counter that counts the number of clock cycles and another performance counter that counts the number of instructions issued could be read. By reading the values in the performance counters, the designer can gain a better understanding of how efficiently microprocessor resources are used.
However, performance counters require dedicated hardware for each event that may be counted. Because microprocessors are typically not redesigned and fabricated prior to each test a performance counter must be available for every event that may be counted. However, some events may never be of interest to designers or may be examined only rarely. Thus, resources are consumed by performance monitoring that may be rarely or never used, leading to a waste of microprocessor resources, which are often scarce. It would be desirable to avoid having to have dedicated performance monitoring circuitry for events that may be of little or no interest.
The present invention provides a dynamically configurable centralized performance monitoring architecture that counts events that occur in various distributed circuits of a microprocessor without having to incorporate performance counters for each of these circuits.